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Nikhilam Sutra
Inglese
91 b
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A multiplier is one of the key hardware blocks in most digital signal processing systems. With advances in technology, many researchers have tried to design multipliers which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. In this work, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on Ancient Indian Vedic Mathematics. The Vedic mathematics approach is totally different and considered very close to the way a human mind works. This work gives information of "Nikhilam Sutra" which can increase the speed of multiplier by reducing the number of iterations. Vedic Mathematics also suggests one more formulae for multiplication i.e. "Urdhva Tiryakbhyam" algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers.
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