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Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design, 1
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This book offers readers a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today s multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. He then describes out-of-order parallel discrete event simulation (Out-of-Order PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays multi-core PCs. This approach enables readers to design simulators that exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.
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